Computers with memory arrays are used in a wide variety of applications including mainframe computers, personal computers, washing machines, kitchen appliances, motor vehicles, telephones, answering machines and other applications. A computer is to be understood here in the widest sense as an electronic control device and/or computing device.
The memory arrangement of a computer is used for permanently or temporarily storing data, for example parameters which are necessary for operating the computer, or computing results which are generated by the computer when the computer is operating.
The memory arrangement has a memory with at least one memory cell, generally a plurality of memory cells. Each memory cell has a storage element in which a quantity of electrical charge can be stored in order to set the memory contents of the memory cell.
There are volatile and non-volatile memory cells. In a volatile memory cell, a memory content which is stored in the storage element typically remains for only approximately a second in the storage element. The memory contents must therefore be periodically refreshed. In a non-volatile memory cell, the memory contents which are stored in the storage element remain permanently in the storage element for a storage time of the order of magnitude of years.
A non-volatile MOSFET-based memory cell (MOSFET=metal oxide semiconductor field effect transistor) is based on a MOSFET with a source region, a drain region, a channel region running between the source region and the drain region, a gate electrode (control gate) which is arranged in order to control the channel region, and a gate oxide layer which is arranged between the gate electrode (control gate) and the channel region.
In the non-volatile MOSFET-based memory cell, the gate electrode is used as a control gate. A storage element for storing memory contents of the memory cell is provided between the control gate and the gate oxide layer over the channel region. The storage element has a potential barrier both with respect to the channel region and with respect to the control gate. As a result of the fact that a suitable electrical voltage which is sufficiently high in terms of absolute value is applied to the control gate, electrical charge carriers can be charged from the channel region into the storage element, or can be discharged from the storage element into the channel region. As a result, memory contents of the memory cell can either be programmed or erased.
An example of a non-volatile memory is the EEPROM (Electrically Erasable Programmable Read Only Memory). In an EEPROM, programmed memory contents can be erased again by applying an electrical voltage.
Non-volatile MOSFET-based memory cells are, in terms of design, floating gate memory cells and MIOS memory cells (MIOS=metal insulator oxide semiconductor.
In a floating gate memory cell the storage element is formed by a metallically conductive floating gate.
In a MIOS memory cell, the storage element is formed from an insulator storage element made of (at least) one insulator material. The memory contents of the storage element are formed by a quantity of charge of electrical charge carriers which are trapped in the insulator storage element.
In order to program a MOSFET-based memory cell it is necessary to maintain an electrical current in the channel region of the MOSFET.
To be able to use and operate a memory cell efficiently, efforts are made to reduce the power consumption when the memory cell is programmed.
K. Naruke, S. Yamada, E. Obi, S. Taguchi and M. Wada, “A new flash-erase EEPROM cell with a sidewall select-gate on its source side”, Tech. Digest, 1989, IEDM, pp. 25.7.1–25.7.4 discloses a floating gate memory cell. The memory cell from K. Naruke et al. has a source region, a drain region, a channel region, a storage element array with a floating gate and a control gate arranged over it as well as a source-end lateral select gate provided next to the storage element array. In order to program the memory cell from K. Naruke et al., a comparatively low voltage is applied to the select gate to generate a small electrical flow of current in the channel region. An electrical voltage is applied to the control gate, said electrical voltage being sufficiently high to charge electrical charge carriers into the floating gate. In the memory cell from K. Naruke et al., the electrical voltage applied to the select gate can be significantly lower than the voltage which is necessary to charge the floating gate. As a result, it is possible to program with a lower current than in a floating gate memory cell without a select gate. The voltage for the select gate must, on the other hand, be selected to be sufficiently large here for electrical charge carriers to be able to pass from the source region into the channel region so that a continuous electrically conductive channel is formed between the source region and the drain region.
On the other hand, in order to increase the efficiency of the memory cell or of an array of memory cells, attempts are made to achieve the highest possible integration density, i.e., to accommodate as much individual memory content items per unit area or per unit volume.
For this purpose, the structure size of each individual memory cell is typically reduced.
U.S. Pat. No. 6,335,554 B1 discloses a non-volatile semiconductor memory in which a first gate region section which is arranged above a first ONO storage layer and above a source region, a second gate region section which is arranged above a second ONO storage layer and above a drain region, and a third gate region section which is arranged above a channel region and above a gate-insulating layer are provided, the first, second and third gate region sections being electrically connected to one another.
In addition, DE 10036911 A1 (application date: 28 Jul. 2000, date laid-open: 14 Feb. 2002) proposes a memory cell with two ONO storage layers, one of which adjoins a source region and the other a drain region. The conductivity of a channel region is controlled by means of a gate region which is arranged over it as well as by means of two lateral gate components which are connected to the gate region via a connecting line, a gate-insulating layer being arranged between the channel region and the gate region.